1. Field of the Invention
The present invention relates generally to an inkjet head, and more particularly to an inkjet head including a channel substrate in which individual liquid chambers separated by liquid chamber partition walls and communicating with respective ink supply ports are arranged in a widthwise direction of the inkjet head; diaphragms defining the surfaces of the individual liquid chambers facing toward nozzle orifices provided in the individual liquid chambers; and actuators each formed of stacked layers of a lower electrode, a piezoelectric element, and an upper electrode on the corresponding diaphragm.
2. Description of the Related Art
Conventionally, inkjet heads configured to cause liquid to be ejected from microscopic nozzles formed in individual liquid chambers by causing variations in pressure in the individual liquid chambers and recording apparatuses having such inkjet heads are known.
Multiple systems for causing variations in pressure in the individual liquid chambers of inkjet heads have been reduced to practice and commercialized. Examples of such systems include thermal inkjet systems that vaporize liquid by providing a heater in the individual liquid chambers and systems with actuators provided in the individual liquid chambers. Examples of systems with actuators, which vary depending on types of actuators, include piezoelectric element systems and electrostatic systems.
Although it is possible to support inks of a wide variety of physical properties with systems using actuators, it has been considered difficult to increase the arrangement density of individual liquid chambers or reduce head size with systems using actuators. In recent years, however, techniques for increasing the arrangement density of individual liquid chambers using a MEMS (Microelectromechanical System) process have been being established. That is, it is possible to increase the arrangement density of individual liquid chambers by stacking a diaphragm, electrodes, a piezoelectric body, etc., on the individual liquid chambers using a thin film deposition technique and patterning individual piezoelectric elements and interconnects using a semiconductor device manufacturing process (photolithography).
The lower electrode, piezoelectric body, upper electrode, etc., of a piezoelectric element, which are formed using a thin film deposition process as described above, are difficult to stack into layers of 5 μm or more in film thickness. It is necessary for an electrode material to be 1 μm or less in thickness in view of process cost.
In particular, in the piezoelectric body, which is deposited as a film by a thin film deposition process, degradation due to the process environment of photolithography (including temperature and process gas) or degradation due to the number of times of driving, temperature, humidity, etc., tends to be more conspicuous than in the bulk.
It is believed that the degradation is caused by the oxygen deficiency of perovskite oxide, which is widely used as a piezoelectric material, or the diffusion of an element such as Pb. It is considered effective against this degradation to use electrically conductive oxide materials, etc., as electrode materials. However, such oxide materials have problems such as high electrical resistance and high contact (connection) resistance with an interconnect material (metal).
Further, an increase in the density of the piezoelectric elements makes it difficult to establish contact (connections) between the upper electrodes and individual electrode interconnects led out from the upper electrodes to individually drive the piezoelectric elements. At the same time, there is the effect of a voltage drop in the upper electrodes caused by an increase in the resistance of the upper electrodes due to reduction in film thickness and reduction in size. Therefore, there is the issue of the uniform driving of the piezoelectric elements.
The easiest way to address these issues is to stack a metal layer on the upper electrodes. This, however, has the problem of an increase in process cost and the above-described problem of the degradation of the piezoelectric body.
With respect to reduction in interconnect (wiring) resistance, for example, Patent Document 1 listed below describes a technique related to a common electrode. Patent Document 1 illustrates controlling a voltage drop among elements due to the resistance of a common electrode and reducing variations among the elements by increasing the number of contacts of the common electrode and providing bypass interconnects using a lead-out interconnection process. Further, Patent Document 2 listed below describes forming interconnects using a process for forming a led-out interconnect from each longitudinal end of a piezoelectric element.
Further, in the case of using a piezoelectric element formed by a thin film deposition process, the diaphragm is a thin film of a few μm in thickness. Therefore, there is a problem in that the diaphragm is likely to be deformed by residual stress due to stacking the piezoelectric element on the diaphragm. Further, since a substrate in which a channel is formed is reduced in thickness, ensuring strength and improving process accuracy in a manufacturing process have become an issue. As measures for addressing these issues, techniques using a holding substrate have been proposed as described in Patent Documents 3 through 5 listed below.
Patent Documents 3 and 4 describe patterning a multilayer structure including electrodes in a region opposed to a partition wall. Patent Document 5 listed below describes controlling the deflection of diaphragms by forming vibration chambers in a holding substrate, and grinding a channel plate and forming liquid chambers in the channel plate by etching after joining the holding substrate and the channel plate.    [Patent Document 1] Japanese Laid-Open Patent Application No. 2007-118265    [Patent Document 2] Japanese Laid-Open Patent Application No. 2004-154987    [Patent Document 3] Japanese Laid-Open Patent Application No. 2004-082623    [Patent Document 4] Japanese Laid-Open Patent Application No. 2005-144847    [Patent Document 5] Japanese Laid-Open Patent Application No. 11-291497